AR# 51402

7 Series Integrated Block for PCI Express v1.6 - Incorrect RX_CM_TRIM setting for Artix-7 FPGAs

描述

This article describes an incorrect Artix-7 GTP Transceiver setting by the PCIe core v1.6 or earlier thatmay causePCI Express link training problems.

解决方案

The PCI Express core v1.6 or earliersets the RX_CM_TRIM[3:0] attribute incorrectly to 3'b010 (250 mV common mode). This should be updated to the correct setting of 4'b1010 (800 mV common mode) when RX_CM_SEL[1:0] = 2'b11 (programmable).

This will be fixed in a future version of the PCI Express core.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47852 7 Series FPGAs GTP Transceivers - Known Issues and Answer Record List N/A N/A
AR# 51402
日期 08/27/2012
状态 Active
Type 综合文章
器件
IP