AR# 51402: 7 Series Integrated Block for PCI Express v1.6 - Incorrect RX_CM_TRIM setting for Artix-7 FPGAs
7 Series Integrated Block for PCI Express v1.6 - Incorrect RX_CM_TRIM setting for Artix-7 FPGAs
This article describes an incorrect Artix-7 GTP Transceiver setting by the PCIe core v1.6 or earlier thatmay causePCI Express link training problems.
The PCI Express core v1.6 or earliersets the RX_CM_TRIM[3:0] attribute incorrectly to 3'b010 (250 mV common mode). This should be updated to the correct setting of 4'b1010 (800 mV common mode) when RX_CM_SEL[1:0] = 2'b11 (programmable).
This will be fixed in a future version of the PCI Express core.