描述

解决方案

This logic has been updated in the v2.4 rev3 update (attached at the end of this answer record).

The attached rev3 update also includes the rev2 updates which resolved:

• Issues seen in hardware on cable unplug or reset resulting in failure to establish a link or FCS errors at the MAC level; see (Xilinx Answer 51282).
• BASE-KR Training not completing after reset; see (Xilinx Answer 51312).

The attached rev3 update also includes the rev1 updates which resolved:

• Improved hot-plug capabilities.
• Separation of the tx and rx resets in the example design and block level.
• Updates to improve timing closure in the Vivado tool; see (Xilinx Answer 50809).
• Connection of signal_detect port to core FSMs.

The v2.4 rev3 core is preproduction and hardware testing continues.

To install the patch, follow the instructions in the included readme file.

附件