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AR# 51474

MIG 7 Series Design Assistant - DDR2/DDR3, Termination and I/O Standard Guidelines

Description

The MIG 7 Series DDR2/DDR3 designs are characterized with specific termination schemes and I/O Standards. The DDR2 and DDR3 SDRAM Memory Interface Solution > Core Architecture > Design Guidelines section within the7 Series FPGAs Memory Interface User Guide (UG586) includes information on termination guidelines and the MIG design's use of I/O Standards.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Termination

Running SI Simulation using IBIS Models is strongly recommended for all memory designs. The user guide section noted above includes information on the following:

  • Termination guidelines for uni- and bi-directional signals
  • Where termination resistors should be placed
  • How to properly terminate ODT, CKE, and RESET to adhere to the DDR2 and DDR3 Memory standards initialization processes
  • Usage of ODT (at the memory) and DCI (at the memory)
    • The usage of ODT has many advantages including lower power and better signal for the reads along with fewer components on the board and less chance for manufacturing issues.

Please read the entire section in UG586 noted above for full details.

Addtional Termination Information:

  • (Xilinx Answer 42783) MIG DDR2/DDR3 - Termination for Data Mask (DM) when DM is disabled
  • (Xilinx Answer 41624) 7 Series MIG DDR3 SDRAM - Is external termination on DQ and DQS required in High Range (HR) banks?
  • (Xilinx Answer 41590) 7 Series MIG DDR3 SRAM - What are the DCI VRP/VRN reference resistor values for DDR3 interfaces?
  • (Xilinx Answer 46082) MIG 7 Series DDR3 - How to enable Dynamic ODT Special Use Case (No ODT pin required at FPGA)
  • (Xilinx Answer 47232) MIG 7 Series DDR3L - RESET# recommendations to meet JEDEC standard requirements

I/O Standards

The MIG tool creates the UCF using the appropriate standard based on input from the GUI. You can find the MIGUCF in either the "example_design/par" or "user_design/par" directories. Only the I/O standards provided in the MIG UCFs have been tested in hardware during MIG characterization.

Revision History
08/24/12 - Initial Release

    链接问答记录

    主要问答记录

    Answer Number 问答标题 问题版本 已解决问题的版本
    51475 MIG 7 系列设计助手 - MIG 7 系列 DDR2/DDR3、电路板布局和设计指南 N/A N/A

    子答复记录

    Answer Number 问答标题 问题版本 已解决问题的版本
    41624 7 Series MIG DDR3 SDRAM - Is external termination on DQ and DQS required in High Range (HR) banks? N/A N/A
    AR# 51474
    创建日期 08/24/2012
    Last Updated 10/17/2013
    状态 Active
    Type 解决方案中心
    器件
    • Artix-7
    • Kintex-7
    • Virtex-7
    IP
    • MIG 7 Series