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AR# 51553

Design Advisory Master Answer Record for LogiCORE IP Aurora 8B10B and Aurora 64B66B

Description

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. 

解决方案

For a list of all current Release Notes and Known Issues for Aurora 8B10B IP, please refer to the IP Release Notes Guide:

http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Design Advisory Alerted on January 21, 2013:

01/21/2013 (Xilinx Answer 53304) Design Advisory for Aurora 8B10B v8.3 - OOB attribute settings update for 7 series GTX/GTH Transceivers and Zynq-7000 SoC Transceivers

Design Advisory Alerted on October 28, 2013:

10/28/2013 (Xilinx Answer 51554) Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs

Design Advisory Alerted on August 3, 2015:

08/03/2015 (Xilinx Answer 64793) Design Advisory for Aurora 8B10B v11.0 (or) earlier - Artix-7 GTP - Simplex RX core is not de-asserting MMCM Reset and as a result RXRESETDONE is not HIGH

Design Advisory Alerted on May 9, 2016:

05/09/2016 (Xilinx Answer 66963) Design Advisory for Aurora 8B10B v11.0 Rev2 or later - Artix-7 GTP - Channel up toggles periodically for Verilog IP


Revision History:

01/21/2013 Initial release
10/28/2013 Updated DAAR#51554
08/03/2015 Updated DAAR#64793
05/09/2016 Updated DAAR#66963

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
21263 Aurora Solution Center N/A N/A

子答复记录

AR# 51553
日期 05/05/2016
状态 Active
Type 设计咨询
IP
  • Aurora 8B/10B
  • Aurora 64B/66B
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