UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51597

Endpoint Block Plus Wrapper for PCI Express - Master Answer Record

Description

This master answer record for the Virtex-5 Endpoint Block Plus Wrapper for PCI Express core lists all release notes, Design Advisories, Known Issues and general information answer records for different versions of the core.

_________________________________________________
This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express

解决方案

Release Notes:

(Xilinx Answer 23985) Release Notes v1.1
(Xilinx Answer 24603) Release Notes v1.2
(Xilinx Answer 25162) Release Notes v1.3
(Xilinx Answer 25493) Release Notes v1.4
(Xilinx Answer 29468) Release Notes v1.5
(Xilinx Answer 30120) Release Notes v1.6
(Xilinx Answer 30632) Release Notes v1.7
(Xilinx Answer 30980) Release Notes v1.8
(Xilinx Answer 31572) Release Notes v1.9
(Xilinx Answer 32274) Release Notes v1.10
(Xilinx Answer 32741) Release Notes v1.11
(Xilinx Answer 33278) Release Notes v1.12
(Xilinx Answer 33762) Release Notes v1.13
(Xilinx Answer 35321) Release Notes v1.14
(Xilinx Answer 42760) Release Notes v1.15

Design Advisories:

(Xilinx Answer 33580) Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record
(Xilinx Answer 34444) Design Advisory for the Endpoint Block Plus Wrapper v1.13 for PCI Express - Transmit Stall Due to Link Partner Advertisement of Data Limited Completion Credits
(Xilinx Answer 33699) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Polarity Reversal on Lane 7 Could Cause the Core Not to Train all 8 Lanes
(Xilinx Answer 33534) Design Advisory for the Endpoint Block Plus for PCI Express Wrapper v1.12 for PCI Express - Using Synplify with the Block Plus Wrapper Source Code Delivery
(Xilinx Answer 33411) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - After warm reset, TX direction stalls forever because of deassertion of trn_tdst_rdy_n
(Xilinx Answer 33709) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Improve Timing Closure
(Xilinx Answer 33710) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Extended deassertions of trn_rnp_ok_n could result in completions being blocked inside the core


Known Issues/General Information:

(Xilinx Answer 30124) Endpoint Block Plus Wrapper for PCI Express - Patch updates for Endpoint Block Plus Wrapper for PCI Express
(Xilinx Answer 31164) Endpoint Block Plus Wrapper v1.8 for PCI Express - MPS of 128 or 256 bytes causes received TLP bit errors due to Expansion ROM work-around
(Xilinx Answer 31460) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - The default TXPREEMPHASIS value is incorrect for FXT devices on page 7 of the CORE Generator Customization GUI
(Xilinx Answer 32091) Endpoint Block Plus Wrapper v1.11 for PCI Express - Downstream Port model drops completions with length 64 bytes and greater
(Xilinx Answer 32727) Endpoint Block Plus Wrapper v1.11 for PCI Express - MAP fails to complete due to predictable IP placement constraints
(Xilinx Answer 32946) Endpoint Block Plus Wrapper v1.11 for PCI Express - Syntax error in x1 board_dual.v causes simulation failures
(Xilinx Answer 33850) Endpoint Block Plus Wrapper v1.13 for PCI Express - Reading and Writing Configuration Space Registers Fails
(Xilinx Answer 34706) Endpoint Block Plus Wrapper v1.15 for PCI Express - Disconnecting Packets on TX Interface when Interfacing with a link Partner Advertising Non-Infinite Completion Credits Can Eventually Stall the Transmit Interface
(Xilinx Answer 37246) Endpoint Block Plus Wrapper v1.14 for PCI Express - Possible inbound packet loss if a 8b10b error occurs while previous packet is being written into receive block RAM
(Xilinx Answer 31210) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Interrupt Status bit not set when generating Legacy Interrupt
(Xilinx Answer 31211) Endpoint Block Plus Wrapper v1.12 for PCI Express - Link transitioning to L0s causes BAR settings to be reset
(Xilinx Answer 31646) Endpoint Block Plus Wrapper v1.14 for PCI Express - Dual core UCF problems
(Xilinx Answer 31647) Endpoint Block Plus Wrapper v1.12 for PCI Express - Dual core implement_dual.bat file missing
(Xilinx Answer 31843) Endpoint Block Plus Wrapper v1.9 for PCI Express - Power management transition from D0 to D3hot to D0 can cause transmit stall
(Xilinx Answer 31850) Endpoint Block Plus Wrapper v1.12 for PCI Express - Simulation testbench writes to incorrect address for Device Control Register
(Xilinx Answer 33400) Endpoint Block Plus Wrapper v1.12 for PCI Express - ModelSim simulation results in numerous signals trimmed from the wave dump
(Xilinx Answer 33401) Endpoint Block Plus Wrapper v1.12 for PCI Express - "ERROR:sim:159 - An internal error has occurred - when disabling TX_DIFF_BOOST
(Xilinx Answer 33410) Endpoint Block Plus Wrapper v1.12 for PCI Express - Compatibility issues with ISE Project Navigator because of PIO_EP.v file module declarations and 64-bit interface ifdef declaration
(Xilinx Answer 33421) Endpoint Block Plus Wrapper v1.11 for PCI Express - Core generated for x2 lanes, Virtex-5 FXT or TXT, will not link up
(Xilinx Answer 33937) Endpoint Block Plus Wrapper for PCI Express - The implement.sh[bat] file errors out during synthesis of the wrapper files
(Xilinx Answer 33939) Endpoint Block Plus Wrapper v1.12 and later for PCI Express - How to create an NGC file of the Block Plus Wrapper files
(Xilinx Answer 51600) Endpoint Block Plus Wrapper v1.15 for PCI Express - Example Design Simulation Fails for x8 Configuration Article
(Xilinx Answer 42368) Virtex-5 Integrated PCI Express Block Plus - Debugging Guide for Link Training Issues
(Xilinx Answer 46888) Virtex-5 Endpoint Block Plus for PCI Express - Debugging and Packet Analysis Guide with Downstream Port Model and PIO Example Design
(Xilinx Answer 47109) Virtex-5 Endpoint Block Plus for PCI Express - Value for cfg_interrupt_mmenable signal Article
(Xilinx Answer 30107) Endpoint Block Plus Wrapper for PCI Express - What output should be expected when running the PIO example simulation?
(Xilinx Answer 31376) Endpoint Block Plus Wrapper v1.8 for PCI Express - Transmit Lockup on First Completion Transmitted after Link Up
(Xilinx Answer 31419) LogiCORE Endpoint Block Plus for PCI Express - ML555 not recognized by system. What is the pinout for the ML555 board?
(Xilinx Answer 31704) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Importing a v1.8 XCO to v1.9 causes "Error:sim228 -An Invalid core configuration has been detected during Customization.
(Xilinx Answer 34183) Endpoint Block Plus Wrapper v1.13 for PCI Express - How to generate an NGC from the source files
(Xilinx Answer 29236) Endpoint Block Plus Wrapper for PCI Express - How should the user application respond to requests targeting Expansion ROM? System hangs during Boot process
(Xilinx Answer 31284) Endpoint Block Plus Wrapper v1.9 for PCI Express - Per Vector Masking Bit incorrectly set inside MSI Control Register
(Xilinx Answer 32270) Endpoint Block Plus Wrapper v1.9 for PCI Express - Using non-synchronous links with Virtex-5 FXT (GTX RocketIO) could result in data errors
(Xilinx Answer 33643) Endpoint Block Plus Wrapper v1.12 for PCI Express - Cannot implement the core in Project Navigator
(Xilinx Answer 36783) Endpoint Block Plus Wrapper v1.14 for PCI Express - Finite completion attribute not set correctly

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
N/A N/A
N/A N/A
67815 [Synth 8-4169] error in use clause: package 'vcomponents' not found in library 'xpm' N/A N/A
67818 Zynq UltraScale+ MPSoC: 2016.3 PMUFW Loading via JTAG / SD Boot Modes and Running An Example N/A N/A
67819 Zynq UltraScale+ MPSoC: 2016.3 PMUFW, How to add custom initialization code. N/A N/A
N/A N/A
67449 High Speed SelectIO Wizard - How to create multiple instances of the same setup N/A N/A
67442 JESD204B - A simplified approach to achieving robust repeatable latency N/A N/A
67440 AXI Bridge for PCI Express Gen3 (Vivado 2016.1) - [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'axi_pcie3_0'. Failed to generate 'Examples' outputs: N/A N/A
674 SPROMS, Markings - The XC1700 Ordering ID (part number) and PROM Marking ID are different for the same part N/A N/A
N/A N/A
67544 DDR4/DDR3 UltraScale IP - Data errors seen at user interface when using Normal Ordering Error. The errored data presented is correct data from a later read from the same address. App_rdy might get stuck low. N/A N/A
67543 Vivado 系统生成器 v2016.2 — 无法通过运行系统生成脚本,在 Ubuntu 14.04 中配置和启动 Matlab。 N/A N/A
67548 ECO : Next Generation FPGA Editor N/A N/A
6768 Virtex/-E/-II/-II Pro/-4/-5 - Are Virtex devices hot-swap compliant? N/A N/A
67684 UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problems N/A N/A
N/A N/A
67780 SDK becomes non-responsive when I try to change the BSP setting on an Ubuntu 14 Virtual Machine N/A N/A
67787 2015.4 Vivado — 实现方案设置改变时,比特流 tcl.post 设置被删除 N/A N/A
N/A N/A
67414 Zynq UltraScale+ MPSoC: 2016.2/2016.1 FSBL unable to load PMU_FW in SD and eMMC boot mode on ZCU102 board N/A N/A
67412 Zynq UltraScale+ MPSoC: 2016.2 FSBL, Added DDR ECC Initialization feature N/A N/A
67416 2016.1 PetaLinux - Installer Automatically Appends Sub-Directory to Target Installation Path N/A N/A
N/A N/A
67922 RLDRAM3 IP - Example Design - Advanced Traffic Generator (ATG) detects data compare errors when testing with the TG_MAX_NUM_OF_ITER_ADDR parameter is set to a large value N/A N/A
67923 2016.2 PetaLinux Zynq UltraScale+ MPSoC GMII2RGMII on MACB driver N/A N/A
6704 3.1i Design Manager - How do I specify files (EDN, EDF, VHD, VER, SCH, etc.) to be automatically copied to my version or revision subdirectories for maintenance? N/A N/A
67041 Soft Error Mitigation (SEM) IP - Using UltraScale SEM IP in Vivado IP Integrator (IPI) N/A N/A
67045 HDMI RX Subsystem - Do the DDC Signals need to be connected if using the HDMI core in DVI only mode without HDCP? N/A N/A
67043 JESD204 v6.1, v6.2, v7.0 and JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - Defaults to DFE Equalisation mode N/A N/A
67044 JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - TXDIFFCTRL low default value N/A N/A
N/A N/A
67141 Simulation Libraries - Can I use UNIMACRO libraries in UltraScale and UltraScale Plus? N/A N/A
67144 UltraScale+ PCI Express Integrated Block (Vivado 2016.1) - Incorrect GT Quad Location for Virtex 9P Devices N/A N/A
67145 Zynq UltraScale+ MPSoC, Vivado 2016.1 - ILA/IBA cores are not found in Vivado Hardware Manager for ZU3 and ZU15 devices N/A N/A
67142 2016.1 - Simulation - Project Utilities Tcl App update required for Export Simulation N/A N/A
6728 1.5i SP2 Virtex Map - Crash during map. N/A N/A
67280 2016.1 Zynq UltraScale+ MPSoC: FSBL fails to load the PMUFW N/A N/A
6738 HP 1.5i Install : 1 archive had fatal errors. file #0. bad zipfile offset (lseek): 0 N/A N/A
67384 Vivado - [Place 30-678] Failed to do clock region partitioning N/A N/A
67382 2016.1 Vivado Simulation - compile_simlib targetting ModelSim DE fails on Linux 64-bit OS N/A N/A
67381 2016.1 Vivado Hardware Manager: Incorrect IDCODES shown in Vivado Hardware Manager GUI for some UltraScale devices N/A N/A
6789 1.5i SpartanXL PAR - Divide by Zero crash N/A N/A
67895 2016.3 Vivado IP Flows - When packaging a block design (BD) containing a MicroBlaze block, I get the warning: CRITICAL WARNING: [IP_Flow 19-4791] Block design with Microblaze subdesign IP 'my_design_microblaze_0_0' should be packaged with the XCI option N/A N/A
67892 QuestaSim - Fatal: (vsim-12005) Undefined function '_ZN5boost6system15system_categoryEv' introduced from '/Xilinx/VIVADO/Vivado/2016.1/lib/lnx64.o/librdi_commonxillic.so' is being called N/A N/A
67893 2016.2 Download - Downloading Vivado on Windows 10, the browser states "The signature of Xilinx_Vivado_SDK_2016.2_0605_1_Win64.exe is corrupt or invalid" N/A N/A
67890 2016.3 - Vivado Simulator - Scope for pre-compiled IP instance is missing in Scope Window N/A N/A
67891 DDR4/DDR3 IP - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode N/A N/A
6752 *Obselete* 1.5i JTAG Programmer - SP2 Patch update-9500XL/Win95 error when programming (Error:basut - Check the target power supply is stable...) N/A N/A
67522 SDSoC - SDDebug and SDRelease build configurations decoupled N/A N/A
67523 SDSoC - Passing command line arguments to executable with Performance Estimation N/A N/A
67520 MIG 7 Series DDR3 - Periodic reads used for VT tracking might be missing during continuous write transactions N/A N/A
67528 How to speed up "10G/25G Ethernet Subsystem" simulation N/A N/A
67521 SDSoC - SDSoC 2016.2 - Release Notes and Known Issues N/A N/A
6782 NGDBUILD netlist priority: What's the searching order NGDBUILD uses to merge hierarchical modules into a .ngd file N/A N/A
67820 Zynq UltraScale+ MPSoC: 2016.3 PMUFW, Error Management N/A N/A
67828 Zynq UltraScale+ MPSoC: Linux SPI interrupts mapping N/A N/A
67824 2016.2 Virtex UltraScale+ - Clock Placer can fail to partition UltraScale+ designs due to not properly accounting for PS8 blocks interference with clock routing N/A N/A
6749 Virtex Configuration - The DONE pin does not go High, and the INIT pin does not go Low N/A N/A
67499 2016.2 Vivado - Loading a synthesized or implemented design in Vivado gives an Internal Exception and the error message "Xgd File 'xc****.xgd' is missing" N/A N/A
67491 High Speed SelectIO Wizard - Unable to select the SLVS IOSTANDARD N/A N/A
671 Error cl192 or cl126 while converting a PALASM (PDS) file N/A N/A
N/A N/A
67558 Vivado - ERROR: [Project 1-589] Checkpoint part '(part name)-es2' is not available. Closest-matching available part(s): (part name) N/A N/A
67553 2016.2 - SDSoC - ZC706_mem platform failing N/A N/A
67551 Vivado Simulator does not give any warning or error message when an integer goes out of range N/A N/A
N/A N/A
67796 ERROR: [VRFC 10-449] cannot open file "/afs/xxxx/obsfdacmj4ltsh34hqceamceyrcimraog5opt0hdnxd.sdb" for writing N/A N/A
67793 MIPI CSI-2 Receiver Subsystem v2.0 (Rev. 1) - Why do I see timing failing on the video_aresetn when using two CSI-2 Receiver Subsystems with one as a master and one as a slave? N/A N/A
6701 VERILOG-XL - How do I run simulation with Verilog-XL? N/A N/A
67013 2016.1 - compile_simlib fails with 3-4 errors for all simulators when the -ise_install_path option is used N/A N/A
67010 Vivado HLS 2016.1 : Why does the perfect loop example have poorer performance versus the imperfect loop example? N/A N/A
67015 2016.1 - compile_simlib - Abnormal program termination (EXCEPTION_ACCESS_VIOLATION) N/A N/A
67012 2016.x Vivado Simulator - Known Issues N/A N/A
N/A N/A
67420 2016.2 XEN test is not working on Zynq UltraScale+ MPSoC boards in QEMU N/A N/A
67426 SDSoC - Cannot debug application when targeting a custom platform N/A N/A
67421 DMA Subsystem for PCI Express (Vivado 2016.2) - Prefetchable support for 64-bit BAR N/A N/A
67422 UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2016.2) - Link up failure after multiple resets N/A N/A
67427 Zynq UltraScale - How can I debug a Linux application running on a Zynq UltraScale QEMU N/A N/A
679 Obselete : Could not get model for statbar! N/A N/A
N/A N/A
67938 2016.X - Simulation - ModelSim generates error when simulating XPM N/A N/A
67936 Vivado - ERROR: [Project 1-202] Error writing the XML file 'Z:/eda/myproj/myproj.xpr' N/A N/A
67933 UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part. N/A N/A
67931 1G/2.5G Ethernet PCS/PMA or SGMII v15.2 - SGMII over LVDS option is not enabled in GUI for devices which do not have Transceivers N/A N/A
67939 Soft Error Mitigation (SEM) IP – Location of the makedata.tcl file has changed in Vivado 2016.3 N/A N/A
67930 2016.2 PetaLinux Zynq UltraScale+ MPSoC GEM Clock Control needs to set for EMIO clock for RX N/A N/A
6709 FPGA Configuration - Done pin does not go high, Startup block is used N/A N/A
67098 2016.1 UltraScale Implementation - New DRC check for clock routing in UltraScale results in both new positive and false-positive errors. N/A N/A
67097 Vivado Device Programmer - 2016.1 VU440 BBR programming failure N/A N/A
6715 2.1i Template Manager - Selecting "List Options" produces msg. - "Cannot find this file. Please verify that the correct filename and path are given" N/A N/A
67159 2016.1 Petalinux-tools - ATF can be built in OCM or DDR using PetaLinux tools N/A N/A
67158 2016.1 PetaLinux - Petalinux-package command allows PMUFW to be included in the boot image N/A N/A
67150 2016.1 - Simulation Libraries - Compiling Simulation Libraries also includes IP N/A N/A
67155 How to handle TXPIPPMEN in GTY and GTH UltraScale HSSIO N/A N/A
67156 PetaLinux 2016.1 - Product Update Release Notes and Known Issues N/A N/A
N/A N/A
67256 40G/50G Ethernet Sub-System - 2016.1 - How can the core be targeted to Kintex UltraScale/ Kintex UltraScale+ devices N/A N/A
67254 Vivado 2016.1 write_bitstream: Issue configuring 7 Series SSIT designs when porting from 2015.4 to 2016.1 N/A N/A
AR# 51597
创建日期 09/03/2012
Last Updated 01/28/2016
状态 Active
Type 综合文章
IP
  • Virtex-5 Endpoint Block Plus Wrapper for PCI Express ( PCIe )