This section of the MIG 7 Series Design Assistant focuses on Supported Features for the MIG 7 Series designs. In this answer record you will find information related to the following:
NOTE: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Supported Memory Devices
The MIG 7 Series tool allows users to customize the target memory interface by selecting the memory device and data width. The data width can be changed (up to 72 bits) when multiple memory components are used to increase the width of the interface. MIG 7 Series includes a range of memory parts including component, SODIMM, UDIMM and RDIMM. If the specific memory device you are using is not listed, the "Create Custom Part" option is available to manually configure the device. When a custom part is used, you must identify a "base part" that matches your memory device's data width and memory depth. The "Create Custom Part" GUI requires that you enter a number of timing parameters that are available in the device data sheet. The supported range for each parameter is what is listed in the "Create Custom Part" GUI. For further details on specifying a memory device in the MIG 7 Series tool, see "Creating 7 Series FPGA DDR3 Memory Controller" in The 7 Series FPGAs Memory Interface User Guide.
For a list of supported memory devices, see (Xilinx Answer 45195) MIG 7 Series - Release Notes and Known Issues for All Versions. Dual rank support for DDR3 was added in MIG 1.6, available with ISE Design Suite 14.2.
The MIG 7 Series tool should be used to validate whether the target memory interface and data rate can be supported in the target FPGA device and bank configuration. Support is affected by FPGA speed grade, package, family, Vccaux_io, I/O bank usage, and target memory device.
The MIG 7 Series tool allows multi-controller designs be generated containing DDR3, QDRII+, and/or RLDRAMII. Up to 8 controllers of either DDR3, QDRII+, RLDRAMII or a combination of these can be designed within the tool. During bank selection, the tool recognizes whether the number of controllers specified can fit in the selected FPGA device. The DDR3 and DDR2 Memory Interface Solution > Getting Started section of The 7 Series FPGAs Memory Interface User Guide discusses generation of multi-controllers.
For information on clocking and the ability to share resources between controllers, see (Xilinx Answer 40603).
For information on sharing banks across controllers, see (Xilinx Answer 41706).
For information on JEDEC specification, see (Xilinx Answer 51684).