The following flow hangs when I run an application that uses a PL peripheral via any AXI port (for example, trying to access the PL @ 0x40000000 via M_AXI_GPx port):
connect arm hw
source ps7_init.tcl
ps7_init
mrd 0x40000000 1
Starting from ISE Design Suite 14.2, the ps7_init.tcl does NOT enable the level shifters. Also, in 2.0 silicon, the boot ROM does not bring the PL out of reset anymore.
It is up to the FSBL, or the user in case of the XMD flow, to enable the level shifter and to bring the PL out of reset after the bitstream is downloaded.
XMD FLOW
The command called "init_user" takes care of the following steps:
Program PS_LVL_SHFTR_EN to 0x0000000F
Program FPGA_RESET_REG to 0x0
This is the new XMD flow starting in 14.2:
fpga -f system.bit
connect arm hw
source ps7_init.tcl
ps7_init
init_user
FSBL FLOW
The following lines of code are used in the FSBL after the download of the bitstream (for both 1.0 and 2.0 silicon):
FsblOut32(PS_LVL_SHFTR_EN, 0x0000000F)| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 52540 | Zynq-7000 SoC - Frequently Asked Questions | N/A | N/A |
| 50863 | Zynq-7000 SoC - 调试 | N/A | N/A |
| AR# 51807 | |
|---|---|
| 日期 | 04/19/2013 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |
| Tools | |