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AR# 51836

Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Aggregate Data Types

Description

This Answer Record describes SystemVerilog Aggregate Data Types supported by Vivado Synthesis and also provides coding examples for them. These coding examples are attached to this answer record. The AR also contains information related to known issues and good coding practices.
 
Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs covered in each example.

解决方案

SystemVerilog Aggregate Data Types that are supported by Vivado Synthesis.
 
Please refer to Table 1-1 at the end of this AR for the coding examples for Aggregate Data Types.
 
1. Structure.
Vivado Synthesis supports usage of the struct data type defined in System Verilog. A structure is a collection of data that can be referenced all at once or by accessing the individual members of the structure. This is similar to the VHDL concept of a record. This can be declared with the help of the typedef keyword which is supported in Vivado Synthesis.
 
Syntax:
typedef struct {struct_member1; struct_member2;...struct_memberx;} structure_name;
 
Example:
typedef struct {
bit [7:0] opcode;
bit [23:0] addr;
} instruction; // named structure type
instruction IR; // define variable
....
IR.opcode = 1; // set field in IR
 
2. Union.
Vivado Synthesis supports usage of the union data type defined in System Verilog. A union is a data type comprising of multiple data types. Only one data type is used at a time.
This is useful in cases where the data type changes depending on how it is used. This can be declared with the help of the typedef keyword which is supported in Vivado Synthesis.
 
Syntax:
typedef union (union_member1; union_member2;...union_memberx;} union_name;
 
Example:
typedef union {
int i;
shortreal f;
} num; // named union type
num n; //define variable
....
n.f = 0.0; // set n in floating point format
 
3. Arrays.
Vivado Synthesis supports SystemVerilog Packed and Unpacked Arrays.
 
3.1 Packed Array
A packed array is a mechanism for subdividing a vector into subfields which can be conveniently accessed as array elements. Packed arrays refer to the dimension declared before the object name. Packed arrays can only be made of the single bit types (bit, logic, int etc.,),  and recursively other packed arrays and packed structures. Packed arrays are guaranteed to be laid out contiguously in memory.
 
Example:
logic [5:0] sig1; //packed array
 
Data types with predetermined widths do not need the packed dimensions declared.
 
Example:
byte c2; // same as bit [7:0] c2;
integer i1; // same as logic signed [31:0] i1;
 
3.2 Unpacked Array
An unpacked array can be of any type unlike Packed Arrays. Unpacked arrays refer to the dimensions declared after the object name. When assigning to an unpacked array, the source and target must be arrays with the same number of unpacked dimensions, and the length of each dimension must be the same. Assignment to an unpacked array is done by assigning each element of the source unpacked array to the corresponding element of the target unpacked array. Unpacked arrays are not arranged contiguously in memory.
 
Example:
logic sig2 [5:0]; //unpacked array
 
Coding Examples for Aggregate Data Types 
Table 1-1
Coding Example Name Construct Used
 aggregate_data_types_example1.zip
  • parameter
  • always procedural block
  • block statements
  • operators : && , unary
  • unpacked array
 aggregate_data_types_example2.zip
  • parameter
  • always procedural block
  • block statements
  • operators : && , unary
  • packed array
 aggregate_data_types_example3.zip
  • data type :logic
  • always_ff procedural block
  • struct
  • operators : +
 data_types_example4.zip
  • data type :logic
  • always_ff procedural block
  • union
  • operators : ==

Attachments

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Answer Number 问答标题 问题版本 已解决问题的版本
51360 Design Assistant for Vivado Synthesis - Help with SystemVerilog Support N/A N/A
AR# 51836
创建日期 09/15/2012
Last Updated 04/03/2013
状态 Active
Type 解决方案中心
Tools
  • Vivado Design Suite