This answer record describes SystemVerilog Connecting Module feature and Interface structures supported by Vivado Synthesis and also provides some coding examples for them. These coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

 

Please refer to Table 1-1 at the end of this AR for the coding examples for the related coding examples.

 

1. Connecting Modules.
Vivado Synthesis supports the following four ways to instantiate and connect modules.

• by ordered list
• by name
• by named ports
• by wildcard ports

 

2. Interfaces.
Interfaces are a way of specifying communication between blocks. An interface is a group of nets and variables that are grouped together for the purpose of making connections between modules. Vivado Synthesis supports the following interfaces structures:

• Interface definition ports
• Interface data type declarations
• Interface modport definitions
• Interface tasks and functions; must be fully automatic
• Interface procedural code; must follow synthesis rules
• Parameterized Interfaces

 

Coding Example Name	Constructs Used
interfaces_example.zip	interfaces modports tasks in interfaces parameterized interfaces
module_connecting_example.zip	module connecting module connecting with wildcard ports