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AR# 51837

Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Connecting Modules and Interfaces

Description

This answer record describes SystemVerilog Connecting Module feature and Interface structures supported by Vivado Synthesis and also provides some coding examples for them. These coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.
 
Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs covered in each example

解决方案

SystemVerilog Connecting Modules and Interfaces structures that are supported by Vivado Synthesis
 
Please refer to Table 1-1 at the end of this AR for the coding examples for the related coding examples.
 
1. Connecting Modules.
Vivado Synthesis supports the following four ways to instantiate and connect modules.
  • by ordered list
  • by name
  • by named ports
  • by wildcard ports
 
2. Interfaces.
Interfaces are a way of specifying communication between blocks. An interface is a group of nets and variables that are grouped together for the purpose of making connections between modules. Vivado Synthesis supports the following interfaces structures:
  • Interface definition ports
  • Interface data type declarations
  • Interface modport definitions
  • Interface tasks and functions; must be fully automatic
  • Interface procedural code; must follow synthesis rules
  • Parameterized Interfaces
 
Coding Examples for Module connecting and Interfaces
Table 1-1
Coding Example Name Constructs Used
 interfaces_example.zip
  • interfaces
  • modports
  • tasks in interfaces
  • parameterized interfaces
 module_connecting_example.zip
  • module connecting
  • module connecting with wildcard ports

Attachments

文件名 文件大小 File Type
interfaces_example.zip 4 KB ZIP
module_connecting_example.zip 1 KB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
51360 Design Assistant for Vivado Synthesis - Help with SystemVerilog Support N/A N/A
AR# 51837
创建日期 09/15/2012
Last Updated 04/03/2013
状态 Active
Type 解决方案中心
Tools
  • Vivado Design Suite