Version Found: v2.5
Version Resolved and other Known Issues: See (Xilinx Answer 45723)
After a PCIe hot reset, the endpoint does not respond to the host's memory read (MRd).
The MRd does not appear at the AXI RX port.
In Gen2 x8, the MRd does not appear at the AXI RX port because in trn_rx_128.v, one counter (i.e., u_cnt) is not reset by the hot reset.
Fundamentally, u_cnt and b_cnt are covered by different resets.
To work around this issue, make the following modification in the toplevel <component_name>.v file:
Though the issue is found in Gen2 x8, the work-around can be applied to all configurations.
09/05/2013 - Initial release