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AR# 5193

LogiCORE PCI - How does the LogiCORE PCI interface handle master aborts (abnormal terminations)?


General Description:

How does the LogiCORE PCI interface handle master abort situations?


A master may terminate a PCI transaction when it has completed its intended transaction; it may also use a timeout when the master's GNT# line is de-asserted and its internal latency timer expires.

The mechanism used for a master-initiated termination is when FRAME# is de asserted and IRDY# is asserted. This condition signals to the target that the final data phase is in process. The final data phase occurs when both IRDY# and TRDY# are asserted. The transaction reaches completion when both FRAME# and IRDY# are de asserted (idle state).

The master may also terminate a transaction when no target responds. This is known as a "master abort". Typically, after the master asserts the FRAME# signal and drives the address onto AD signal lines, one of the targets can claim the access cycles by asserting the DEVSEL# signal within a predetermined number of clock cycles. The earliest a master can abort a transaction is five clocks after the FRAME# was first sampled asserted. The master can wait longer than that and must support the FRAME#--IRDY# relationship on all transactions, including master aborts. The master must assume that the target of the access is incapable of dealing with the requested transaction or the address was bad and must not repeat the transaction.

A host bus bridge must return all 1's on a read transaction and discard all the data on a write transaction when terminated with a master abort. The bridge must set a master abort detected bit in the status register. Other master devices may report this condition as an error by signaling the SERR# when the master cannot report that error through its device driver.

The LogiCORE PCI will dessert FRAME_IO after not receiving a DEVSEL_IO from the addressed target.

The LogiCORE initiator will set the bit CSR[29] if it receives a master abort on a transaction it initiated. It will also assert CSR[39] on the clock cycle after the initiator determines that the addressed target has not responded to the transaction request. if it detects a master abort on the PCI bus. The LogiCORE interface then uses this information to signal to the state machine that a master abort has occurred.

AR# 5193
日期 12/15/2012
状态 Active
Type 综合文章