描述

解决方案

This is because the cache is enabled by default in standalone BSP.

There are a few ways to achieve the desired outcome.

1) Disable the cache in main.c code; and it should work fine.

#include "xil_cache.h"
Xil_DCacheDisable();

2) In the selftest example, flush the cache after writing to the DDR and before continuing to the next step.

for ( Index = 0; Index < CIP_AXI4_MASTER_SELFTEST_BUFSIZE; Index++ )
{
SrcBuffer[Index] = Index;
DstBuffer[Index] = 0;
}

xil_printf(" ******* flushing data cache!!! \n\r");
Xil_DCacheFlushRange((unsigned int)SrcBuffer, CIP_AXI4_MASTER_SELFTEST_BUFSIZE);
Xil_DCacheFlushRange((unsigned int)DstBuffer, CIP_AXI4_MASTER_SELFTEST_BUFSIZE);

xil_printf(" - start user logic master module to receive word from the source\n\r");

3) "Only" flush the src buffer, then start the cip and finally invalidate the destination buffer just before doing the compare to force reading from the main DDR (rather than the cache).

for ( Index = 0; Index < CIP_AXI4_MASTER_SELFTEST_BUFSIZE; Index++ )
{
SrcBuffer[Index] = Index;
DstBuffer[Index] = 0;
}

xil_printf(" ******* flushing data cache for source only!!! \n\r");
Xil_DCacheFlushRange((unsigned int)SrcBuffer, CIP_AXI4_MASTER_SELFTEST_BUFSIZE);
xil_printf(" - start user logic master module to receive word from the source\n\r");
/**** more code from selftest ****/

xil_printf(" ******* invalidate destination data cache to force correct read!!! \n\r");
Xil_DCacheInvalidateRange((unsigned int)DstBuffer, CIP_AXI4_MASTER_SELFTEST_BUFSIZE);
/*** do the memory compare as in the original code ***/