I have done my design in a 3rd party tool targeting a Xilinx part, and have gone through the Xilinx tools and now I want to do a Board Level Timing Simualation. Is this possible?
Yes this is possible doing the following:
1) Create the Board level schematic. On the symbol for the Xilinx component make sure to add the following properties to the instance:
lca_technology to the target architecture, ie XC4000e, of type string.
MODEL xilinx_simtype of type expression so that this can be dynamically changed between functional and timing.
2) Be sure to run ngd2edif -v mentor, or if using the GUI make sure to choose the option for 'Quicksim' in the Implementation->Options, Simulation dialogue box when processing the design.
3) Run pld_edif2tim on the Xilinx FPGA design.
4) After creating the board level schematic with the symbol for the Xilinx FPGA on it, run 'xbvpt -t' -t for timing, on the board design. This will write Xilinx-specific properties into the board-level viewpoint.
5) Run regmodel to register the EDDM model with the component using regmodel -t, on the Xilinx component. If you used pld_edif2tim defaults, then you will run regmodel on designname_lib/designname/view_1
You are now ready to run Quicksim II for Timing simulation.
NOTE: For a more detailed description of the flow, scripts, and usage, please use (Xilinx solution 2560). This will all the scripts, the usage, and flows, for running a functional and timing board level simulation.