UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

的页面

AR# 51999

14.2 SysGen - Does the FIR Compiler v6.3 block enable the 'reset data vector' option?

Description

The FIR Compiler v6.3 allows you to enable a reset signal, but it does not allow you to specify whether you reset the data vector or not (reset_data_vector option in CORE Generator). Further, there is nothing documenting whether or not this option is enabled.

解决方案

System Generator does indeed enable the reset_data_vector option. Thus the data path will be cleared upon reset at the cost of increased resource utilization. Future versions of the FIR Compiler documentation outline that this is enabled.
AR# 51999
日期 06/05/2013
状态 Active
Type 综合文章
Tools
  • System Generator for DSP
  • System Generator for DSP - 14
  • System Generator for DSP - 14.1
  • System Generator for DSP - 14.2
IP
  • FIR Compiler