AR# 52014

Zynq-7000 AP SoC, Boot IOP - Quad-SPI MIO pin 8 is inadvertently enabled during boot

描述

The Quad-SPI I/O interface can optionally use MIO pin 8 as a feedback output clock to enable the interface to be clocked at high frequency. The BootROM inadvertently and unnecessarily enables MIO pin 8 as a toggling output during a Quad-SPI boot sequence.

解决方案

The BootROM operates the Quad-SPI below the frequency where the feedback output clock is required. The MIO pin 8 is actively driven with the Quad-SPI clock toggling High and Low. The feedback output clock must be allowed to freely toggle.

Impact:	Minor..
Work-around:	Board designs should account for MIO pin 8 being an output that toggles during a Quad-SPI boot sequence and take appropriate action.
Configurations Affected:	Systems that use the Quad-SPI boot mode.
Device Revision(s) Affected:	Refer to Zynq-7000 Device Advisory Master Answer Record

本答复记录是否对您有帮助？

AR# 52014
日期	10/25/2012
状态	Active
Type	设计咨询
器件	Zynq-7000

的页面

AR# 52014

Zynq-7000 AP SoC, Boot IOP - Quad-SPI MIO pin 8 is inadvertently enabled during boot

描述

解决方案

应用

产品

开发者专区

技术支持

关于 Xilinx