These Release Notes are for the XADC Wizard v2.3, released in Vivado 2012.3 tools, and contain the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
- Device Support
The XADC Wizard v2.3 supports the 7 series and Zynq devices. You can use the Wizard to customize the I/O Ports usage, the User Alarms and Thresholds, and the Channel Sequencer.
New Features in v2.3
Added AXI4Lite interface support in v2.3
Bug Fixes in in v2.3
Both Known issues with the v2.2 core are fixed in v2.3.
Removed the issues on setup time while running timing simulation of XADC Wizard example designs. Also resolved is the issue with the incorrect INST cell name in the Verilog core.
Known Issues v2.3
If preforming a timing simulation for XADC wizard v2.3 when AXI-4Lite interface is selected, the simulation will fail. This is due to the same sampling event used for both timing and functional simulation in the testbench.
9/28/2012 - Initial Release