AR# 52099

MIG 7 Series - Incorrect behavior when using Synplify with a MIG design that uses the I/O Low Power feature

描述

Version Found: MIG 7 Series v1.6
Version Resolved: See (Xilinx Answer 45195)

When the MIG 7 Series FPGAs DDR3 design with the I/O Low Power feature enabled is synthesized using Synplify 2012.09, Synplify inserts an OBUF at the top level, then an IOBUFT_DCIEN lower in the hierarchy. 

This creates redundant buffers. 

When this netlist is implemented in Vivado, the following error occurs:

[Place 30-49] I/O port: ddr3_dqs_p[0] is an output but has an IOStandard of DIFF_SSTL15_T_DCI which can only support bidirectional ports

When implemented with the ISE tool, NGDBuild removes the redundant OBUF and errors similar to the Vivado flow do not occur:

INFO:NgdBuild:649 - Removing redundant 'OBUF' symbol 'ddr3_dqs_p_obuf[3]'. All constraints associated with this symbol will be ignored.

This error does not occur if Synplify is set to NOT insert I/O buffers.

解决方案

Background

This error occurs because Synplify is currently missing the timing model for the IOBUFDS_DCIEN primitive. 

Because of this, the primitive becomes a blackbox and output buffers get inserted.

Work-around

To work around this issue until Synplify includes the timing models and prevent OBUF insertion, attributes similar to the following can be applied in the synthesis constraint file:

define_attribute {p:ddr3_dqs_n[3:0]} {syn_insert_pad} {0} define_attribute {p:ddr3_dqs_p[3:0]} {syn_insert_pad} {0}


AR# 52099
日期 08/14/2014
状态 Active
Type 已知问题
器件
IP