AR# 5213


1.5i/2.1i: TRCE reports large differences in clock delay (skew) on BUFGLS in XV devices


General Description: TRCE reports large delays for specific longlines

in the 4000XV devices.


In the 1.5i speed files for the XV devices there is an incorrect parameter

value. This causes the delays associated with specific longlines to have

the incorrect delay.

This is can be resolved by installing the latest speed file updates. They

are available on the Xilinx FTP Site:

For the Workstation:

For the PC:

AR# 5213
日期 01/18/2010
状态 Archive
Type 综合文章
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