AR# 52147


MIG 7 Series DDR3 - tRFC and tRAS simulation errors occur during calibration when running at or below 400 MHz


Version Found: MIG 7 Series v1.7
Version Resolved: See (Xilinx Answer 45195)

If simulating a MIG 7 Series FPGA DDR3 design running at or below 400 MHz, tRFC and tRAS max violations can occur before calibration completes that are similar to the following:

"# sim_tb_top.mem_rnk[0].mem.gen_mem[0].*.cmd_task: at time 112279326.0 ps ERROR: tRFC maximum violation during No Op # sim_tb_top.\mem_rnk[0].gen_mem[0].*.chk_err: at time 134531257.0 ps
ERROR: tRAS maximum violation during Precharge to bank 0 "

These violations appear before calibration is completed.


The violations occur due to a wait period during the DQS_FOUND stage of calibration and can be safely ignored.

Revision History
10/16/2012 - Initial release

AR# 52147
日期 02/07/2013
状态 Active
Type 已知问题
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