Version Found: MIG 7 Series v1.7
Version Resolved: See (Xilinx Answer 45195)
When ChipScope analyzer is added into the MIG 7 Series design, Vivado Design Suite generates the following critical warnings during synthesis:
CRITICAL WARNING: [Synth 8-3321] create_clock attempting to set clock on an unknown port/pin for constraint at line 2 of /proj/ipmig/pboya/mig/mig_7series_v1_7/GUI_Testing/072012/mig_7series_v1_7/example_design/par/proj1.srcs/sources_1/ip/ddr_icon/ddr_icon.constraints/ddr_icon.xdc.
CRITICAL WARNING: [Synth 8-3321] create_generated_clock attempting to set clock on an unknown port/pin for constraint at line 3 of /proj/ipmig/pboya/mig/mig_7series_v1_7/GUI_Testing/072012/mig_7series_v1_7/example_design/par/proj1.srcs/sources_1/ip/ddr_icon/ddr_icon.constraints/ddr_icon.xdc.
These warnings can be ignored.
Revision History
10/16/2012 - Initial release
AR# 52181 | |
---|---|
日期 | 02/18/2013 |
状态 | Active |
Type | 已知问题 |
器件 | |
IP |