I want to submit my Vivado design project to Xilinx for testing or to reproduce an issue I have seen. However, I would rather not provide the full design as is, due to proprietary concerns.
Is there a way to create a version of my design that has the logic stripped out?
You can use the logic_function_stripped option when writing out either a checkpoint or EDIF file. All logic equations should be turned to XORs and all RAMs will have their contents zero out.