AR# 52197


Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Operators


This answer record describes SystemVerilog Operators supported by Vivado Synthesis and also provides coding examples for them. The coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs demonstrated in each example.


SystemVerilog Operators that are supported by Vivado Synthesis
Please refer to Table 1-1 at the end of this AR for the coding examples.
The SystemVerilog operators are a combination of Verilog and C operators. In both languages, the type and size of the operand is fixed, hence the operator is of a fixed type and size. The fixed type and size of operator is preserved in SystemVerilog.

1.Assignment Operators.

In addition to the simple assignment operator "="

For example:
a[i]+=2; // same as a[i] = a[i] +2;

SystemVerilog includes C assignment operators and special bitwise assignment operators: +=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, and >>>=. An assignment operator is semantically equivalent to a blocking assignment, with the exception that any left hand side index expression is only evaluated once.

2.Binary Operators.

When a binary operator has one operand of type bit and another of type logic, the result is of type logic. If one operand is of type int and the other of type integer, the result is of type integer. The operators != and == return an X if either operand contains an X or a Z, as in Verilog-2001. This is converted to a 0 if the result is converted to type bit, for example, in an if statement. The unary reduction operators (& ~& | ~| ^ ~^) can be applied to any integer expression (including packed arrays). The operators shall return a single value of type logic if the packed type is four valued, and of type bit if the packed type is two valued.

int i;
bit b = &i;
integer j;
logic c = &j;             

3.Conditional Operator.
Operator used for conditional statements.
conditional_expression ::= cond_predicate ? { attribute_instance } expression : expression

4.Concatenation Operator.

Braces ( { } ) are used to show concatenation as in Verilog. The concatenation is treated as a packed vector of bits. It can be used on the left hand side of an assignment or in an expression.

logic log1, log2, log3;
{log1, log2, log3} = 3b111;
{log1, log2, log3} = {1b1, 1b1, 1b1}; // same effect as 3b111

Coding Examples for Operators

Table 1-1
Coding example name Operators Used
  • Assignment Operators (+=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, >>>=)
  • Binary Operators (+, -, *, /, %, ==, ~=, ===, ~==, &&, ||, **, < , <=, >, >=, &, |, ^, ^~, ~^, >>, <<, >>>, <<<)
  • Conditional Operator (? :)
  • Concatenation Operator ({...})


文件名 文件大小 File Type 1 KB ZIP 487 Bytes ZIP 915 Bytes ZIP 919 Bytes ZIP



Answer Number 问答标题 问题版本 已解决问题的版本
51360 Design Assistant for Vivado Synthesis - Help with SystemVerilog Support N/A N/A
AR# 52197
日期 04/03/2013
状态 Active
Type 解决方案中心
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