AR# 52232


MIG 7 Series RLDRAM 3 - tWTR and tRC violations are reported during simulations for 4:1 mode (CMD_PER_CLK=4) and Burst Length 2 (BL=2) configurations


Version Found: v1.7
Version Resolved: See (Xilinx Answer 45195).

For MIG 7 Series RLDRAM 3 4:1 BL2 interfaces, the memory model may report tWTR and tRC violations during simulation.


There is no work-around at this time. For assistance, please contact Xilinx Technical Support.

Revision History
10/16/2012 - Initial release

AR# 52232
日期 02/07/2013
状态 Active
Type 已知问题
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