You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-KR) v2.4 - Updates to Training block needed for tx output training by the far-end device to complete
In the Ten Gigabit Ethernet PCS/PMA (10GBASE-KR) v2.4 core, updates to the Training block are needed for tx output training by the far-end device to complete:
- Adjustment needed for Training block to meet 802.3 electrical specification for increments and decrements.
- Update to not reset Training block with general reset.
- Connection to RXSLIDE input to GT Instance needed to allow Training to work.
- New ports needed (coeff_minus_1, coeff_zero and coeff_plus_1) to connect to the GT to control the TX wave-shaping filter coefficients.
- Update needed to DRP register locations for Training.
The changes have been incorporated in the v2.5 core which is included in ISE 14.3/ Vivado 2012.3.
Characterization on the training block is still being completed.
- 10 Gigabit Ethernet PCS-PMA with FEC/Auto-Negotiation for backplanes (10GBASE-KR)
- Ten Gigabit Ethernet PCS/PMA