This answer record covers known issues with version 2.3 of the 7 Series FPGAs Transceivers Wizard targeting GTZ Transceivers in Vivado 2012.3.
Port and Attribute Changes:
if (rx_data_aligned != bram_data_r)
Change this to:
if (rx_data_aligned != bram_data_c)
set_property LOC BUFGCTRL_X0Y14 [get_cells -hier -filter {name =~*drpclk0_buf}]
CTLE tuning:
In addition to the port and attribute changes to the 2012.3 Wizard mentioned above, the CTLE needs to be tuned.
For details on the CTLE tuning procedure, refer to the 7 Series FPGAs GTZ Transceiver User Guide (UG478 v2.0 or later).
Note: The "Version Found" lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions. This is an issue with latency of the core.
AR# 52261 | |
---|---|
日期 | 06/21/2017 |
状态 | Active |
Type | 已知问题 |
器件 | |
Tools | |
IP |