We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5229

LogiCORE PCI - How do the REQ#/GNT#/RST# lines in the LogiCORE interface act?


General Description:

How do the REQ#/GNT#/RST# lines in the LogiCORE interface act?


PCI bus masters are linked to the central arbiter by individual request (REQ#) and grant (GNT#) signals. Every master has its own REQ# and GNT# lines.

A PCI bus master will request ownership of the PCI bus by asserting the REQ# line when it is immediately ready to begin a bus transaction. The arbiter will grant access to an agent by asserting its GNT# line. REQ# is an input to the arbiter while GNT# is an output.

The REQ# signal must be 3-stated and GNT# ignored when the RST# (reset) signal has been asserted. The arbiter can only perform arbitration after the RST# line has been de-asserted.

The RST# signal is used to bring PCI-specific registers, sequencers, and signals to a consistent state. Anytime RST# is asserted, all PCI output signals must be driven to a benign state.

The LogiCORE interface uses the REQ_O signal to request access to the bus. The Initiator may only request the bus when it has been enabled by setting the Bus Master Enable bit (CSR2).

The GNT_I signal is used by LogiCORE to indicate the arbiter has granted the bus. If GNT_I is asserted and there is not a pending REQUEST or the Bus Master Enable bit is not set, then the interface performs bus parking.

The LogiCORE uses RST_I input to reset all internal flip-flops and force all outputs to a high-impedance state: it uses the dedicated global set/reset and global 3-state functions of the FPGA; it resets the contents of the Command/Status Register; it disables the Initiator functionality until the system software sets the Bus Master Enable bit (CSR2) in the Command Register; it disables memory or I/O Target accesses until the system software sets the Memory Enable or I/O Enable bits in the Command Register.

The REQUEST line is used by the user application to request a PCI initiator transaction. The Bus Master Enable bit (CSR2) must be set in the Command Register before REQUEST has any affect on the PCI32 interface. This should be done by the system configuration software. The Initiator functionality is disabled at power-on after RST_I is asserted. REQUEST should be driven by the user interface for one clock cycle to request the bus.

The signal CFG_SELF signals the LogiCORE that the configuration command is intended for the core itself (intended for host bridge applications). The assertion of CFG_SELF, high will override the Master Enable bit (CSR2) as well as perform a simultaneous Initiator and target transaction to allow the user application access to the internal LogiCORE configuration space. CFG_SELF must be asserted at the same time as REQUEST and must be kept asserted until the transaction is complete, which is signaled by the de-assertion of M_DATA signal.

AR# 5229
日期 12/15/2012
状态 Active
Type 综合文章