The following is an example of memory created using record type:
subtype DATA_TYPE is std_logic_Vector(DATA_WIDTH-1 downto 0);
type MEM_WORD is
record
data : DATA_TYPE;
end record MEM_WORD;
type MEM_DATA_ARRAY_TYPE is array (natural range <>) of MEM_WORD;
Vivado Synthesis does not infer a block RAM in the above example as it does not support memory models that are created using VHDL record type.
This issue will be fixed in a future release.
To work around this issue, modify the HDL to avoid using a record type, as in the following example:
subtype DATA_TYPE is std_logic_Vector(DATA_WIDTH-1 downto 0);
type MEM_DATA_ARRAY_TYPE is array (natural range <>) of DATA_TYPE;
AR# 52331 | |
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日期 | 04/18/2014 |
状态 | Active |
Type | 综合文章 |
Tools |