AR# 52343

14.2 SysGen - Incorrect VHDL when using multiple AXI FIFOs

描述

I have a sysgen design that has multiple instances of the AXI FIFOs (with TLAST signals enabled). However, when I generate the code and try to synthesize, I get errors. I tracked down the failure to the FIFO generator entity declaration. It seems to create bad VHDL:
 
entity xlaxififogen_my_test is
  generic (
    core_name0: string := "";
    tdata_width: integer := -1;
    tdest_width: integer := -1;
    tstrb_width: integer := -1;
    tkeep_width: integer := -1;
    tid_width: integer := -1;
    tuser_width: integer := -1;
    has_aresetn: integer := -1
  );
  port (
      s_aclk: in std_logic;
      ce: in std_logic;
      aresetn: in std_logic;
      s_axis_tdata: in std_logic_vector(tdata_width - 1 downto 0);
      s_axis_tlast: in std_logic;
      m_axis_tdata: out std_logic_vector(tdata_width - 1 downto 0);
      m_axis_tlast: out std_logic;
      s_axis_tdata: in std_logic_vector(tdata_width - 1 downto 0);
      s_axis_tlast: in std_logic;
      m_axis_tdata: out std_logic_vector(tdata_width - 1 downto 0);
      m_axis_tlast: out std_logic;
      s_axis_tvalid: in std_logic;
      s_axis_tready: out std_logic;
      m_axis_tready: in std_logic;
      m_axis_tvalid: out std_logic
  );
end xlaxififogen_my_test;

As you can see, many of the signals are declared multiple times which lead to the XST errors.

解决方案

This is a known issue, discovered in the 14.2 tools and resolved in 14.4 and later builds.

If unable to upgrade to a later version, then the workaround is to simply comment out the extraneous port declarations.
AR# 52343
日期 06/03/2013
状态 Active
Type 综合文章
Tools
IP