The following DRC error occurs with timing simulation of Aurora 64B66B core v7.1:
"# DRC Error : Reset is unsuccessful at time 11637984. RST must be held high for at least three RDCLK clock cycles, and RDEN must be low for four clock cycles before RST becomes active high, and RDEN remains low during this reset cycle."
This answer record provides a fix for this issue.
RD_EN and WR_EN provided to FIFO in the CBCC module need to be delayed by a few cycles to meet the requirement.
Please replace <USER_COMPONENT_NAME>\src\<USER_COMPONENT_NAME>_cbcc _gtx_6466.v[hd] file with the files attached to this answer record.
For Single lane designs: aurora_64b66b_v7_3_cbcc_gtx_6466.v[hd]
For Multilane designs: multilane_aurora_64b66b_v7_3_cbcc_gtx_6466.v[hd]
Update the component name of the module in-line with the generated design.
10/12/2012 - Initial release