AR# 52390

MIG 7 Series RLDRAM II / 3 - user_addr assignment incorrect in example_top module

描述

Version Found: v1.7
Version Resolved: See (Xilinx Answer 54025)

The full address range cannot be accessed due to incorrect assignment to user_addr in the example_top module. This will affect the traffic generator module when trying to access the upper bounds of the address space.

解决方案

To work around this issue, the following RTL changes can be made inside example_top.v.

Change:

assign user_addr[0+:ADDR_WIDTH] = tg_addr[ADDR_WIDTH-1:TG_A_START];

To:

assign user_addr[0+:ADDR_WIDTH] = tg_addr[TG_A_START+:ADDR_WIDTH];

Revision History
10/01/2013 - Initial release

AR# 52390
日期 10/01/2013
状态 Active
Type 已知问题
器件
IP