The root port configuration is not supported on the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 core. Users trying to load an old project with root port configuration in CORE Generator will run into an error.
This is a known issue and is scheduled to be fixed in a future release of the core.
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.