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AR# 52458

2012.3 Vivado Implementation Tools - Clock Placer can only support up to 32 BUFG components on an XC7V2000T (SSI device), even though more exist on the device.

描述

The Vivado implementation tools are currently unable to "segment" the routing resources for clocks between layers of silicon on SSI devices. For this reason, the tools do not support the use of more than 32 BUFGs and do not support the use overlapping BUFG sites (same site used on different silicon levels).

解决方案

This limitation will be removed in VivadoDesign Suite2012.4 where clock segmentation will be supported.
AR# 52458
日期 01/23/2013
状态 Active
Type 版本说明
器件
  • Virtex-7
Tools
  • Vivado - 2012.3
的页面