AR# 52468


Zynq-7000 - AxSIZE Port Width Mismatch Between Zynq AXI Interface and AXI Protocol


The AXI Protocol states that AWSIZE/ARSIZE are 3-bits wide. 

However, the Zynq Processing System AXI Interface with the PL suggests that these signals are only 2-bits wide.

Why does the Zynq PS not follow the AXI Protocol?



The Zynq AXI Interfaces do adhere to the AXI Protocol.  

However, due to the nature of the Interfaces and their respective data widths, only 2-bits are required for AxSIZE signals.

Per Chapter 5 of UG585 : Zynq Technical Reference Manual the Interfaces and their respective AxSIZE widths are as follows:

Zynq AXI Interface AxSIZE Width (bits) Data Width (bits)
M_AXI_GP{0:1} AxSIZE[1:0] 32
S_AXI_GP{0:1} AxSIZE[1:0] 32
S_AXI_HP{0:3} AxSIZE[1:0] 32 / 64
S_AXI_ACP AxSIZE[1:0] 64

The values above correspond to the Unisim Macro Instantiation for the Zynq Processing System (PS).  

This instantiation is the common element for all Zynq designs. 

It can be found at the following location for ISE: <path>\Xilinx\14.x\ISE_DS\ISE\verilog\src\unisims\PS7.v

From the values above, it is clear that the maximum data width for the AXI Interfaces is 64-bits.  

Per the AXI Protocol Specification, AxSIZE of 2'b11 corresponds to a transfer size of 64-bits.  

Considering the Zynq-7000 Interfaces will never have a data width above 64-bits, it is not necessary to use the most significant bit of AxSIZE.  

Therefore, this bit will be masked off in HDL for the Zynq PS.

This masking is evident when reviewing the HDL associated with the PS. 

Within PS7.v, the following lines of code appear. 

module PS7(


output [1:0] MAXIGP0AWSIZE;




Moving to the PS HDL wrapper  <path>\Xilinx\14.x\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_vx\hdl\verilog\processing_system7.v

module processing_system7(


output [2:0] M_AXI_GP0_AWSIZE,

... );


assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};


PS7 PS7_i (



... );



AR# 52468
日期 10/14/2014
状态 Active
Type 综合文章
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