AR# 52486


Zynq-7000 - Need to Confirm Values Set in Translation Tables for Zynq Board Support Package


The DDR region for translation_table.s is configured as 0x15DE6. Is it possible to confirm what the following bits in this page table section correspond to?

In translation_table.s:

.rept 0x0400 /* 0x00000000 - 0x3fffffff (DDR Cacheable) */
.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
.set SECT, SECT+0x100000


Note: All page and table designations are in reference to ARM DDI 0406B version of ARM Architecture Reference Manual.

Information regarding appropriate page table section settings in the Board Support Package (BSP) Translation Tables will require investigation beyond Xilinx documentation.

The Xilinx documentation for Zynq SoC does not cover certain aspects because it is already defined by ARM. To confirm the values of the DDR section values in translation_table.s, it is necessary to reference both ARM and Xilinx documentation.

In this case, the ARM document that needs to be referenced is the ARM Architecture Reference Manual (AARM). It can be found on ARM's website. First time users will need to register to log in.

Once AARM is opened, look back at the DDR table entry. An uncommon element that would make for a narrow search is "TEX." One of the first hits for "TEX" in the AARM is a table describing the descriptor formats for a page table section. Below this table are descriptions of each descriptor and reference pages for more information. From here, it is easy to follow the documentation references to determine the values of each descriptor and what they correspond to.

Staying with "TEX" as the example, more information concerning it can be found in the Memory Region Attributes Section. This section provides an encoding table for the "TEX", "C", and "B" descriptors. A value of 0x15de6 corresponds to S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 per the initial table. The encoding table allows users to cross reference the values of descriptors to their corresponding parameter.

Per the encoding for this example:
"TEX" = 3'b101 :Cacheable Memory, Write-Back, Write-Allocate for Outer Cache Attribute<
"C" = 1'b0 and "B" = 1'b1 : Write-Back, Write-Allocate for Inner Cache Attribute
"S" = 1'b1 : Shareable Memory

Now, cross reference these attributes with Xilinx documentation to determine how they are interpreted by the Xilinx tools.

Refer to section 3.4 L2-Cache of UG585 : Zynq Technical Reference Manual.

Table 3-1 provides an explanation for Cache Controller Behavior during SCU Requests. Find the attributes above in the ARMv7 Equivalent column of this table. A Zynq transaction equivalent of Outer write-back, write-allocate is Cacheable write-back, allocate on read and write.

Therefore, a value of 0x15de6 in the DDR section of the BSP page table corresponds to a transaction of cacheable write-back, allocating on read and write.



Answer Number 问答标题 问题版本 已解决问题的版本
52474 Zynq ARM - Where to Look for Documentation Regarding ARM and Cortex-A9 N/A N/A
AR# 52486
日期 01/20/2013
状态 Active
Type 综合文章
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