The Aurora example design has two Aurora cores connected back to back. The Issue is that FRAME_GEN of DUT1 is transmitting before FRAME_CHECK of DUT2 can receive the data. This is due to pipelining flops introduced to handle slack violations in the core.
Delay the data transmission from FRAME_GEN. Add the following code in the example_design\traffic_gen_check\<componene name>_frame_gen.v module:
reg [6:0] channel_up_dly = 7'd0;
always @ (posedge USER_CLK)
channel_up_dly <= `DLY channel_up_dly;
channel_up_dly <= `DLY channel_up_dly + 1'b1;
//Generate RESET signal when Aurora channel is not ready
assign reset_c = RESET || !(&channel_up_dly);
Note that reset_c wire is OR'd with channel_up_dly not with CHANNEL_UP.
10/29/2012 - Initial Release