AR# 52492


Logicore IP Aurora 8B10B v8.3 - ISE 14.3 - Timing simulation of the IP example design fails when using ISE generated Place and Route netlist


If an ISE generated Place and Route netlist is used to do timing simulation of an Aurora 8B10B v8.3 IP example design, a data error count is observed that results in a TEST FAIL message being issued by the testbench that comes with the Aurora 8B10B core. This answer record provides the solution to resolve this issue.


The Aurora example design has two Aurora cores connected back to back. The Issue is that FRAME_GEN of DUT1 is transmitting before FRAME_CHECK of DUT2 can receive the data. This is due to pipelining flops introduced to handle slack violations in the core.
Delay the data transmission from FRAME_GEN. Add the following code in the example_design\traffic_gen_check\<componene name>_frame_gen.v module:
reg [6:0] channel_up_dly = 7'd0;
always @ (posedge USER_CLK)
channel_up_dly <= `DLY channel_up_dly;
else if(CHANNEL_UP)
channel_up_dly <= `DLY channel_up_dly + 1'b1;
//Generate RESET signal when Aurora channel is not ready
assign reset_c = RESET || !(&channel_up_dly);
Note that reset_c wire is OR'd with channel_up_dly not with CHANNEL_UP.
Revision history:
10/29/2012 - Initial Release
AR# 52492
日期 10/29/2012
状态 Active
Type 综合文章
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