2. 技术支持
  3. AR# 5249: SYNPLIFY: How to preserve a signal through synthesis using the syn_keep attribute?
  4. AR# 52497: Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 (ISE 14.3) - Initial VF and Total VF value of 0 in a physical function is not allowed with SR-IOV enabled

AR# 52497

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Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 (ISE 14.3) - Initial VF and Total VF value of 0 in a physical function is not allowed with SR-IOV enabled

描述

Version Found: v1.3
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

When configuring the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 core in CORE Generator, one can set SR-IOV Capability Structure Initial VF and Total VF to 0 in a physical function with SR-IOV enabled. This is not a supported use case.

解决方案

This is a known issue and is scheduled to be fixed in a future release of the core. In the future release, the ability to set the value of 0 for Initial VF and Total VF, when SR-IOV is enabled, will be disabled.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
10/23/2012 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47441 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 52497
日期 08/26/2013
状态 Active
Type 已知问题
IP
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