This is a known issue and is scheduled to be fixed in a future release of the core. In the future release, the ability to set the value of 0 for Initial VF and Total VF, when SR-IOV is enabled, will be disabled.
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Revision History
10/23/2012 - Initial release
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
47441 | Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 | N/A | N/A |
AR# 52497 | |
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日期 | 08/26/2013 |
状态 | Active |
Type | 已知问题 |
IP |