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AR# 5251

VCS: Assertion failed "qop & arg1->pe.real & 0" at line 583 in file eval.c

Description

Keywords: VCS, Verilog, Virtex, CLKDLL, CLKDLLHF, X_CLKDLL, X_CLKDLLHF

Urgency: Standard

General Description:
When compiling CLKDLL and CLKDLLHF models from the Virtex UNISIMS
and the SIMPRIMS library, VCS will issue a compilation error:

Compiling X_CLKDLL.vmd
Top Level Modules:
X_CLKDLL
1 unique modules to generate
Assertion failed "qop & arg1->pe.real & 0" at line 583 in file eval.c
Failure processing module X_CLKDLL in file X_CLKDLL.vmd line 62
Release VCSi 4.2

解决方案

This is a VCS bug with the real datatype case statement.

case (CLKDV_DIVIDE)
1.5 : divide_type <= 'd3;
2.0 : divide_type <= 'd4;
2.5 : divide_type <= 'd5;
3.0 : divide_type <= 'd6;
4.0 : divide_type <= 'd8;
5.0 : divide_type <= 'd10;
8.0 : divide_type <= 'd16;
16.0 : divide_type <= 'd32;
default : begin
$display("Error : CLKDV_DIVIDE = %f is not 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0.", CLKDV_DIVIDE);
$finish;
end
endcase

VCS 5.0.1a and later versions correct the problem.
Please contact Synopsys support to acquire the latest version of VCS.
AR# 5251
创建日期 08/31/2007
Last Updated 08/25/2003
状态 Archive
Type ??????