描述

The MIG 7 Series DDR3/DDR2 design, starting with v1.7, includes a tempearture monitor system to keep the read DQS centered in the DQ read window across temperature variation. Please see (Xilinx Answer 51687) for details. By default, the example design simulation disables usage of the tempmon block. This answer record shows how to enable the block and load an XADC input file to view the process in simulation.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

The changes made to view the tap updates are as follows:

1. Create an XADC text input file to change the temperature in simulation. See the XADC User Guide for information. Here is a sample:
TIME Temp
00000 85
84000 0

2. Set up a wave.do. The signals of interest are:
add wave -noupdate /sim_tb_top/u_ip_top/u_mig_7series_v1_7/u_mig_7series_v1_7_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0/u_ddr_phy_4lanes/ddr_byte_lane_A/ddr_byte_lane_A/phaser_in_gen/phaser_in/PHASER_IN_INST/COUNTERREADVAL
add wave -noupdate /sim_tb_top/u_ip_top/u_mig_7series_v1_7/u_mig_7series_v1_7_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/tempmon_sample_en
add wave -noupdate /sim_tb_top/u_ip_top/u_mig_7series_v1_7/u_mig_7series_v1_7_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/clk
add wave -noupdate /sim_tb_top/u_ip_top/u_mig_7series_v1_7/u_mig_7series_v1_7_memc_ui_top_std/mem_intfc0/mc0/mc_ref_zq_wip
add wave -noupdate /sim_tb_top/u_ip_top/u_mig_7series_v1_7/u_mig_7series_v1_7_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/tempmon_sel_pi_incdec_r

3. Update the user_design/rtl/clocking/mig_<>_tempmon.v module's instantiation of the XADC blockto add the SIM_MONITOR_FILE parameter used to point to the file. Here is an example:

XADC #(
// INIT_40 - INIT_42: XADC configuration registers
.INIT_40(16'h8000), // config reg 0
.INIT_41(16'h3f0f), // config reg 1
.INIT_42(16'h0400), // config reg 2
// INIT_48 - INIT_4F: Sequence Registers
.INIT_48(16'h0100), // Sequencer channel selection
.INIT_49(16'h0000), // Sequencer channel selection
.INIT_4A(16'h0000), // Sequencer Average selection
.INIT_4B(16'h0000), // Sequencer Average selection
.INIT_4C(16'h0000), // Sequencer Bipolar selection
.INIT_4D(16'h0000), // Sequencer Bipolar selection
.INIT_4E(16'h0000), // Sequencer Acq time selection
.INIT_4F(16'h0000), // Sequencer Acq time selection
// INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
.INIT_50(16'hb5ed), // Temp alarm trigger
.INIT_51(16'h57e4), // Vccint upper alarm limit
.INIT_52(16'ha147), // Vccaux upper alarm limit
.INIT_53(16'hca33), // Temp alarm OT upper
.INIT_54(16'ha93a), // Temp alarm reset
.INIT_55(16'h52c6), // Vccint lower alarm limit
.INIT_56(16'h9555), // Vccaux lower alarm limit
.INIT_57(16'hae4e), // Temp alarm OT reset
.INIT_58(16'h5999), // VBRAM upper alarm limit
.INIT_5C(16'h5111), // VBRAM lower alarm limit
// Simulation attributes: Set for proepr simulation behavior
.SIM_DEVICE("7SERIES"), // Select target device (values)
.SIM_MONITOR_FILE("temp.txt")
)

4. Update the user_design/rtl/core_name.v toforce the tempmon to run in simulation. Here is an example on line 518:
localparam TEMP_MON_EN = "ON"; //(SIMULATION == "FALSE") ? "ON" : "OFF";

5. Run the simulation.You will see from the temperature monitor circuit sends the tap change command to the PHY in two cycles and the changes are reflected in anothertwo cycles, for a total offour cycles. Below is an example screenshot:

52523_sim.JPG

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