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  3. AR# 52531: LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v2.5 - Vivado - 7 Series - Timing errors sometimes seen on path to and from Transceiver

AR# 52531

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LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v2.5 - Vivado - 7 Series - Timing errors sometimes seen on path to and from Transceiver

描述

When using the Ten Gigabit Ethernet PCS/PMA v2.5, timing errors are sometimes seen seen in the example design on paths to and from the 7 Series GTX or GTH transceiver when using Vivado Design Suite 2012.3 .

解决方案

These timing errors do not occur when the GTX or GTH transceiver is locked to a specific location. 

Example constraints are shown below:

set_property LOC GTXE2_CHANNEL_X0Y4 [get_cells ten_gig_eth_pcs_pma_block/gtwizard_10gbaser_i/gt0_gtwizard_10gbaser_i/gtxe2_i]
set_property LOC GTHE2_CHANNEL_X1Y4 [get_cells ten_gig_eth_pcs_pma_block/gtwizard_gth_10gbaser_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i]

AR# 52531
日期 09/08/2014
状态 Active
Type 综合文章
IP
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