AR# 52537


LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR)v2.5 - Block lock FSM could get stuck low if GT reset or unstable clock seen by cable pull detection logic


When using the Ten Gigabit Ethernet PCS/PMA v2.4 rev2, v2.4 rev3 or v2.5 core, it is possible for it to get in a deadlock situation were the block lock FSM is held in reset.

The block level code contains logic to detect a cable pull and also to detect a cable reattachment. 

If a PMA reset is issued or the RX output clock from the GT becomes unstable at the wrong time, it is possible to place that logic into a state where it thinks that a cable reattachment has not occurred, even though it has.

This results in the signal_detect control begin stuck low, and as a result the block lock FSM in the core is held in reset state.


The Rate of occurrence for this issue should be very low. 

The master reset to the core example design can be issued to recover from this.

A more robust update to the code for the cable pull/reattach logic is scheduled for v2.6 of the core, which is to be released in Vivado 2012.4 / ISE Design Suite 24.4.

AR# 52537
日期 09/08/2014
状态 Active
Type 综合文章
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