AR# 52539

Zynq-7000 SoC - Board Design


This answer record contains information useful to PCB layout engineers using the Zynq-7000 SoC device family. 

This answer record includes information vital to successful layout of a Zynq-based PCB as well as information that will ease design and layout efforts.

NOTE: This answer record is part of the Xilinx Zynq-7000 SoC Solution Center (Xilinx Answer 52512). Xilinx Zynq-7000 SoC Solution Center is available to address all questions related to Zynq-7000 SoC.

Whether you are starting a new design with Zynq-7000 SoC or troubleshooting a problem, use the Zynq-7000 SoC Solution Center to guide you to the right information.


Top Answer Records Related to Zynq-7000 SoC PCB Design

(Xilinx Answer 52847) Zynq-7000 - Board Design - Sequencing for SRST and POR Signals
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(Xilinx Answer 51996) Zynq-7000, DDRC - What are the Zynq Processing System DDR data sheet parameters?
(Xilinx Answer 52771) Zynq-7000 Power - Should MIO Bank 1 voltage selection be pulled High to Vcco_MIO0 or Vcco_MIO1?
(Xilinx Answer 5108) FPGA Configuration - What is the status of used I/O for Spartan/Virtex families during configuration?
(Xilinx Answer 3359) IBIS Simulation - What information do IBIS models provide? What is not provided?

Related Documentation



Answer Number 问答标题 问题版本 已解决问题的版本
52512 Xilinx Zynq-7000 SoC Solution Center N/A N/A
52511 Zynq-7000 SoC Design Assistant N/A N/A
53051 Zynq-7000 SoC - PS DDR Controller N/A N/A


AR# 52539
日期 05/28/2018
状态 Active
Type 解决方案中心