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AR# 52540

Zynq-7000 AP SoC - Frequently Asked Questions

描述

This Answer Record contains the Zynq-7000 AP SoC Frequently Asked Questions.

NOTE: This answer record is part of the Xilinx Zynq-7000 AP SoC Solution Center (Xilinx Answer 52512)

The Xilinx Zynq-7000 AP SoC Solution Center is available to address all questions related to Zynq-7000 AP SoC. 

Whether you are starting a new design with Zynq-7000 AP SoC or troubleshooting a problem, use the Zynq-7000 AP SoC Solution Center to guide you to the right information.

解决方案

Top Frequently Asked Questions

(Xilinx Answer 46778) 14.1 EDK, Zynq-7000 - How do I Configure the PS DDRC?
(Xilinx Answer 46881) Zynq-7000 Debug - How do I set up a third-party debug environment on the ZC702 board?
(Xilinx Answer 46871) 14.2 EDK, Zynq-7000 - Which IBIS models should be used for Zynq?
(Xilinx Answer 46988) Zynq-7000 Debug - How do you run ps7_init.tcl from Lauterbach?
(Xilinx Answer 47792) Zynq-7000 EPP, Gigabit Ethernet - What are the supported PHY modes?
(Xilinx Answer 51063) 14.1 Zynq-7000 - Why is QSPI programming not working when the feedback clock is used?
(Xilinx Answer 51248) Zynq-7000 - What QSPI Clock mode/speed is supported on the ZC702?
(Xilinx Answer 51778) Zynq-7000 - How should the PS DDR3 CKE signal be terminated?
(Xilinx Answer 46911) EDK 14.1 Zynq-7000 - How do I create a stub for the second CPU core?
(Xilinx Answer 47167) 14.1 EDK, Zynq - Why can only half of the PS DDR memory be used with MicroBlaze connected?
(Xilinx Answer 51790) Zynq-7000 - How is the DDRC address mapping used?
(Xilinx Answer 50935) Zynq-7000 EPP - Does VCCAUX power the Processor System (PS)?
(Xilinx Answer 50898) 14.1 EDK/SDK - Are there any ECC limitations on the Zynq device DDRx controller?
(Xilinx Answer 51996) Zynq-7000, DDRC - What are the Zynq Processing System DDR data sheet parameters?
(Xilinx Answer 52491) 14.3 EDK, Zynq-7000 - How do I run the Zynq PS-PL AXI interfaces at the highest frequency?
(Xilinx Answer 52252) Zynq-7000 AP SoC ZC702 Evaluation Kit TRD - Why is my 1080p60 input not being detected when using the Avnet IMAGEON FMC daughter card with the 14.1 or 14.2 TRD design?
(Xilinx Answer 50499) 14.2 EDK - Toggling PS_SRST_B does not configure PL when booting from SD or QSPI using BOOT.bin
(Xilinx Answer 51782) EDK-14.3,Zynq-7000: What is the default QSPI interface clock frequency used in the FSBL and How to speed it up?
 
 

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
52512 Xilinx Zynq-7000 AP SoC 解决方案中心 N/A N/A
52511 Zynq-7000 AP SoC Design Assistant N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
46778 Zynq-7000 - How do I configure the PS DDRC board parameters? N/A N/A
46881 Zynq-7000 Debug - How do I set up a third-party debug environment on the ZC702 board? N/A N/A
46871 Zynq-7000 - Which IBIS models should be used for Zynq-7000 devices? N/A N/A
46988 Zynq-7000 Debug - How do you run ps7_init.tcl from Lauterbach? N/A N/A
47792 Zynq-7000 AP SoC, Gigabit Ethernet - What are the supported PHY modes? N/A N/A
51063 14.1 Zynq-7000 - Why is QSPI programming not working when the feedback clock is used? N/A N/A
51248 Zynq-7000 - ZC702 支持什么 QSPI 时钟模式/速度? N/A N/A
51778 Zynq-7000 - How should the PS DDR3 CKE signal be terminated? N/A N/A
46911 EDK 14.1 Zynq-7000 - How do I create a stub for the second CPU core? N/A N/A
47167 14.1 EDK, Zynq - Why can only half of the PS DDR memory be used with MicroBlaze connected? N/A N/A
51790 Zynq-7000 - 如何使用 DDRC 地址映射? N/A N/A
50935 Zynq-7000 AP SoC - Does VCCAUX power the Processor System (PS)? N/A N/A
50898 14.1 EDK/SDK - Are there any ECC limitations on the Zynq device DDRx controller? N/A N/A
51996 Zynq-7000, DDRC - What are the Zynq Processing System DDR data sheet parameters? N/A N/A
52491 14.3 EDK, Zynq-7000 - How do I run the Zynq PS-PL AXI interfaces at the highest frequency? N/A N/A
52252 Zynq-7000 AP SoC ZC702 Evaluation Kit TRD - Why is my 1080p60 input not being detected when using the Avnet IMAGEON FMC daughter card with the 14.1 or 14.2 TRD design? N/A N/A
50499 14.2 EDK – 当您使用 BOOT.bin 从 SD 或 QSPI 启动时,在进行 PS_SRST_B 翻转时将不会对 PL 进行配置。 N/A N/A
51782 EDK-14.3,Zynq-7000 - What is the default QSPI interface clock frequency used in the FSBL and how do I speed it up? N/A N/A
51807 14.2 XMD, Zynq-7000 - Why does the XMD flow hang when I run an application that uses the PL AXI ports? N/A N/A
AR# 52540
日期 05/20/2015
状态 Active
Type 解决方案中心
器件
  • Zynq-7000
的页面