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AR# 52626

7 Series, STARTUPE2 - USRCCLK0 requires three clock cycles to switch CCLK output to User Function

描述

Applying a clock to USRCCLK0 using the STARTUPE2 primitive does not show any response on the external CCLK line for the first few cycles.

Also, if I use the EMCCLK pin to supply a configuration clock source, I see that this clock is still provided on the CCLK pin after the device has configured and DONE has gone High.

Is this expected behavior?

解决方案

The STARTUPE2 primitive will ignore the first three clock cycles after configuration.

However, this behavior is not seen when stopping and starting the clock after the clock is already in use.

These two clock cycles are required to switch the CCLK source from the internal configuration bus to the USERCCLK0 input from FPGA fabric.

When EMCCLK is used as the clock source for configuration, this is an additional concern if the following conditions are met:

  • STARTUPE2 is instantiated
  • USRCCLKTS is set to 0
  • USERCCLK is connected
  • EMCCLK is used as a configuration source


In this case, the three clock cycles are required to switch EMCCLK from clock input to User I/O. 

If USERCCLK0 is gated and no clocks are passed after EOS, then EMCCLK will continue to run on CCLK after configuration completes.

Also, if EMCCLK is used as an I/O in the design, this pin will not switch to User function.

Virtex-6 exhibits the same behavior.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35954 Virtex-5 - USERCLKO and CCLK not synchonised in STARTUP_VIRTEX5 when accessing SPI Flash N/A N/A
AR# 52626
日期 09/21/2015
状态 Active
Type 综合文章
器件
  • Kintex-7
  • Virtex-7
  • Artix-7
  • Virtex-6
的页面