UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5263

VCS - How do I run simulation with VCS?

Description

Keywords: VCS, UniSims, SimPrims, compiled, simulation

Urgency: Standard

General Description:
How do I run a simulation with VCS?

You can run a simulation with VCS in two ways:

- Using library source files with compile-time options
- Using shared pre-compiled libraries

Please see (Xilinx Answer 6330) for information on how to compile the Alliance libraries for VCS.

VCS and VCSi are identical with the exception that VCS is more highly optimized, which results in greater speed for RTL and mixed-level designs. Pure gate-level designs run with comparable speed. VCS and VCSi are guaranteed to provide the exact same simulation results. VCSi is invoked using the "vcsi" command instead of "vcs".

Hereafter, all references to VCS in this document pertain to VCSi as well.

解决方案

1

Using library source files with compile-time options:

Depending upon the makeup of the design (Xilinx instantiated primitives or CORE Generator components), for RTL simulation, specify the following at the command line:

vcs -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/xilinxcorelib \
+incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v \
-Mupdate -R <testfixture>.v <design>.v

For timing simulation or post-NGD2VER, the SimPrims-based libraries are used. Specify the following at the command line:

vcs +compsdf -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v \
+libext+.v -Mupdate -R <testfixture>.v time_sim.v

Please see (Xilinx Answer 6349) for information on back-annotating the SDF file for timing simulation.

The -R option automatically simulates the executable after compilation.

The -Mupdate option enables incremental compilation. Modules will be recompiled for one of the following reasons:

1. The target of a hierarchical reference has changed.
2. A compile time constant, such as a parameter, has changed.
3. The ports of a module instantiated in the module have changed.
4. Module inlining. For example, the merging internally in VCS of a group of module definitions into a larger module definition that leads to faster simulation. These affected modules are again recompiled. (This is performed only once.)

2

Using shared pre-compiled libraries:

Simulation Libraries must be compiled to <compiled_lib_dir> before VCS is used. Please see (Xilinx Answer 6330) for instructions on how to compile the Xilinx Verilog libraries for VCS.

Depending upon the makeup of the design (Xilinx instantiated primitives or CORE Generator components), for RTL simulation, specify the following at the command-line:

vcs -Mupdate -Mlib=<compiled_dir>/unisims_ver -y $XILINX/verilog/src/unisims \
-Mlib=<compiled_dir>/xilinxcorelib_ver - +incdir+$XILINX/verilog/src \
+libext+.v $XILINX/verilog/src/glbl.v -R <testfixture>.v <design>.v

For timing simulation or post-NGD2VER, the SimPrims-based libraries are used. Specify the following at the command-line:

vcs +compsdf -Mupdate -Mlib=<compiled_lib_dir>/simprims_ver \
-y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v +libext+.v \
-R <testfixture>.v time_sim.v

Please see (Xilinx Answer 6349) for information on back-annotating the SDF file for timing simulation.

The -R option automatically simulates the executable after compilation. Finally, the -Mlib=<compiled_lib_dir> option provides VCS with a central
place to look for the descriptor information before it compiles a module and a central place to obtain the object files when it links the executables together.

The -Mupdate option enables incremental compilation. Modules will be recompiled for one of the following reasons:

1. The target of a hierarchical reference has changed.
2. A compile time constant such as a parameter has changed.
3. The ports of a module instantiated in the module have changed.
4. Module inlining. For example, merging internally in VCS a group of module definitions into a larger module definition leads to faster simulation. These affected modules are again recompiled. (This is performed only once.)
AR# 5263
创建日期 12/18/1998
Last Updated 10/09/2003
状态 Active
Type 综合文章