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AR# 52632

Vivado Simulator - How to generate a .saif file for power analysis in Vivado Simulator

描述

How can I generate a .saif file in Vivado XSIM?

解决方案

Follow the steps below to generate the .saif file.
 
1.    Run the post implementation functional simulation using only Verilog netlists, not VHDL.
 
2.    After opening the functional simulation in XSIM, type these commands in the Tcl console:
open_saif
log_saif [get_object /<toplevel_testbench/uut/*>]
run *ns
close_saif

When using the log_saif command it will only log the signals specified in the argument, it does not by default log the signals being seen in the simulation waveform view.

If you wish to observe specific signals or internal signals you need to specifically add them, the following is an example of how to do this:
set top_level [get_obj]
Run this when top_level TB is selected.
set my_int_signal1 [get_objects {/my_TB/uut/Module_1/sub_module1/CLK}]
set my_int_signal2 [get_objects {/my_TB/uut/Module_1/sub_module3/EN}]

set saif_signals [get_obj $top_level $my_int_signal1 $my_int_signal2]
This combines all of the signals defined above into one variable.
log_saif [get_objects $saif_signals]
This will log the combined signals into your .saif file.
run xx ns
close_saif


Alternatively you can do as follows:
log_saif [get_objects $top_level]
log_saif [get_objects $my_int_signal1]
log_saif [get_objects $my_int_signal2]

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 52632
日期 11/18/2014
状态 Active
Type 综合文章
Tools
  • Vivado Design Suite
的页面