We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52645

LogiCORE IP Asynchronous Sample Rate Converter (ASRC) - Does clock jitter affect the ASRC results and can it cause THD glitches?


Does clock jitter affect the ASRC results and can it cause THD glitches?


THD glitches canbe caused by variations/jitter of the clocks, or from other sources, such as problems with the source data or not meeting the clocking requirements documented in the ASRC Product Guide.
First of all,it should beclarified that the clkin and clkout inputs are not clocks in the pure sense, but rather pulsesthat are sampled internally by mclk. Therefore, there is always some jitter on the precise timing of these that is normally filtered out by the ratio tracking logic of the design. It should also be stated that generally a significantamount of jitter on these clocks can betolerated.With that said,large variations on these inputs couldcause THD degradation in some situations.
The exact edge position of clkinis determined by the AES3 RX used, and which clocks it uses. In the case of the design used for verifying that ASRC on Spartan-6 FPGA, the AES3 RX uses a 144 MHz clock that is the CLKFX output of a DCM with a 33 MHz input clock as a reference. It should be noted that the Xilinx AES3 RX reference design from XAPP1015 does not require a synchronous audio clock. What basically happens is that the asynchronous audio input is sampled (oversampled) by a higher frequency clock. The outputs of the AES3 RX, which are used as inputs to the ASRC, are synchronous with the clock going into the AES3 RX. There will always be jitter of a least one clock period on these signals. The ASRC is designed to accommodate this.
The output audio timing, on the other hand, is generally not based on an oversampled asynchronous signal, but rather on a clock synchronous with the audio output. For example, in the Spartan-6 FPGA verificationdesign, there is a 24.576 MHz generated and an external clock module using the CTXIL601 FMC Daughter card. This clock is used to generate the AES3 TX timing. For the ASRC, this clock is divided down to provide the clk_in for the ASRC. For example, for 48 kHz audio output, the 24.576 MHz clock is divided by 512. Therefore, the clk_in signal should have very low jitter, only what is present on the 24.576 clock.

It should also be noted that the measurements in the ASRC Product Guidewere done in the automatic ratio tracking mode. That is, ratio tracking was turned on. These measurements are conducted with jitter intentionally added, and the results were the same. So, as was mentioned before, generally the ASRC can tolerate jitter.

Please see (Xilinx Answer 47209) for a detailed list of LogiCORE IP Asynchronous Sample Rate Converter (ASRC) Release Notes and Known Issues.



Answer Number 问答标题 问题版本 已解决问题的版本
47209 LogiCORE IP Asynchronous Sample Rate Converter (ASRC) - Release Notes and Known Issues N/A N/A
AR# 52645
日期 05/31/2013
状态 Active
Type 综合文章
  • Asynchronous Sample Rate Converter (ASRC)