AR# 52683

AXI Bridge for PCI Express v1.04.a - Latch and Sensitivity List Warning Messages

描述

Version Found: v1.04.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When synthesizing the AXI Bridge for PCI Express v1.04.a core, the tool issues the following warning messages:

WARNING: [Synth 8-614] signal 'cpl_timer_start_count' is read in the process but is not in the sensitivity list
[ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_04_a/hdl/vhdl/axi_slave_read.vhd:979]

WARNING: [Synth 8-327] inferring latch for variable 'first_word_offset_calc_reg'
[ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_04_a/hdl/vhdl/axi_slave_read.vhd:373]

解决方案

This is a known issue to be fixed in the next release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

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链接问答记录

主要问答记录

Answer Number	问答标题	问题版本	已解决问题的版本
44969	AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7	N/A	N/A

AR# 52683
日期	10/31/2012
状态	Active
Type	已知问题
IP	AXI PCI Express (PCIe)

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