AR# 52684


AXI Bridge for PCI Express v1.04.a - Incorrect MSI Message routing in 128-bit mode operation


Version Found: v1.04.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

MSI is incorrectly routed in 128-bit mode operation. This is seen when Normal MWr comes after MSI TLP with a gap of 1 beat.


This is a known issue to be fixed in the next release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.



Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 52684
日期 10/31/2012
状态 Archive
Type 已知问题
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