UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52688

AXI Bridge for PCI Express v1.04.a - Completion TLP not generated when configured as Root Complex on Zynq devices

描述

Version Found: v1.04.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When AXI Bridge for PCI Express v1.04.a core is configured as x4Gen2 Root Port with 128-bit data width, it does not send the CplD TLP in response to a read from the endpoint even after receiving the valid data from AXI side.

解决方案

This is a known issue to be fixed in the next release of the core.

NOTE: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 52688
日期 08/26/2013
状态 Active
Type 已知问题
IP
  • AXI PCI Express (PCIe)
的页面