AR# 52752


14.1 PlanAhead - Simulation operation fails for cores with behavioral models that require MIF files: ERROR: cannot open file 'initfile' (VHDL-1470)


In PlanAhead 14.1 tool, if a core is simulated (using the left hand panel "Run Simulation"), it will fail with a fuse/xelab error during compilation andreport that the model cannot open a file:

ERROR: cannot open file 'initfile' (VHDL-1470)


The wrapper that instantiates the model from XilinxCoreLib does not specify the core generic c_elaboration_dir. This means the MIF file must be present in the work directory of the simulator for it to be able to find it. All file paths in HDL are with respect to the directory where simulation executable was launched (e.g. <projdir>\project_1\project_1.runs\sim_1). The MIF has been generated and can be found in the .srcs directory.

This issue has been fixed in ISE Design Suite 14.2
AR# 52752
日期 11/02/2012
状态 Archive
Type 综合文章
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